The present invention relates to semiconductor memory apparatuses and more particularly, to a semiconductor memory apparatus employing a phase locked loop (PLL) selectively operable in accordance with frequency band.
A known semiconductor apparatus includes a delay locked loop (DLL) circuit to provide an internal clock that precedes a reference clock in a phase by a predetermined amount of time, where the reference clock is obtained by transforming an external clock. The internal clock is usually generated to enable operations in sync with an external clock in a high-density semiconductor memory apparatus such as a synchronous DRAM.
With the trend toward high frequency operation for semiconductor memory apparatuses, the clock frequency of external clocks, as well as the corresponding internal clocks, increases. Thereby, a semiconductor memory apparatus using a conventional DLL circuit becomes unstable in operations of inputting and outputting data in sync with a clock. This is especially true for some semiconductor memory devices used in graphics processes, where data input/output operations become less reliable because of decreasing margins in operational timings between data strobe signals and data.
To alleviate this problem, a semiconductor memory apparatus operating at high frequency is usually associated with a PLL circuit for stabilizing its data input/output operations. A semiconductor memory apparatus employing a PLL circuit for data input does not need to conduct an operation for generating data strobe signals from a clock and latching data. Such a semiconductor memory apparatus including the PLL circuit is used to detect a phase difference between the operational timing of the clock and one of the data and then synchronize the clock and the data by controlling the phase of the data. Therefore, such a semiconductor memory apparatus including the PLL circuit enhances the reliability of the data input operation.
However, such a conventional PLL circuit is only operable in narrow frequency bandwidths. In practice, there is no limit as to the frequency bandwidth in a semiconductor memory apparatus and the signals internally operating therein are modifiable in frequency in accordance with variations of process, voltage, and temperature (PVT).
As such, a PLL circuit operable in only narrow frequency bandwidths is very restrictive and acts as a technical limitation to a semiconductor memory apparatus.